Forum Discussion
PGigl
Occasional Contributor
7 years agoWe are having issue getting data out of the CIC core during simulation.
We have built up a QSYS design with our own core feeding into a CIC core, feeding into a FIR core. In our simulation we can see signals and data going into the core, and see the appropriate handshak...
PGigl
Occasional Contributor
7 years agoRegarding #5, how did you get the example to simulate. The example design did not include a Do file. I ran the TCL script it had created, but was unsure as to the next step. It would be nice if there was a readme file or other instructions, or did I just miss something.
Here is a screen shot of the waveforms.
CheepinC_altera
Regular Contributor
7 years agoHi,
Can you please try the following to see if you are able to get the simulation running after sourcing the TCL script:
1. Type “ld” to start compilation and elaboration
2. Select and add the signals that you would like to monitor to waveform
3. Then type “run -all” to start the simulation
Thank you,.
Best regards,
Chee Pin