Forum Discussion

PGigl's avatar
PGigl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

We are having issue getting data out of the CIC core during simulation.

We have built up a QSYS design with our own core feeding into a CIC core, feeding into a FIR core. In our simulation we can see signals and data going into the core, and see the appropriate handshak...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi Paul, Thanks for your update. Please feel free to update me on my previous inquiries 3 to 5. For your information, I have tested generating an example design with CV with CIC default settings. I am able to run the Modelsim simulation without issue. Thank you
  • PGigl's avatar
    PGigl
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Regarding #5, how did you get the example to simulate. The example design did not include a Do file. I ran the TCL script it had created, but was unsure as to the next step. It would be nice if there was a readme file or other instructions, or did I just miss something.

    Here is a screen shot of the waveforms.

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor
      6 years ago
      Hi, Can you please try the following to see if you are able to get the simulation running after sourcing the TCL script: 1. Type “ld” to start compilation and elaboration 2. Select and add the signals that you would like to monitor to waveform 3. Then type “run -all” to start the simulation Thank you,. Best regards, Chee Pin
    • PGigl's avatar
      PGigl
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      ​Thanks, the example simulates fine..