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PGigl's avatar
PGigl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

We are having issue getting data out of the CIC core during simulation.

We have built up a QSYS design with our own core feeding into a CIC core, feeding into a FIR core. In our simulation we can see signals and data going into the core, and see the appropriate handshak...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi Paul, As I understand it, you are observing some problem when simulating with the CIC IP. To ensure we are on the same page, just would like to check with you on the following: 1. What is the device that you are using? 2. What is the Quartus version that you are using? 3. Would you mind to further elaborate on the unknown output that you are referring to in the initial description? Some screenshots will be helpful for further understanding. 4. Mind share with me the CIC IP configuration ie .ip file will be helpful. 5. Just wonder if you have had any chance to try simulating the example design generated by the IP to see if the simulation is able to run? Please let me know if there is any concern. Thank you. Best regards, Chee Pin
  • PGigl's avatar
    PGigl
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    1. What is the device that you are using? 5CSX

    2. What is the Quartus version that you are using? 18.1 Standard.

    3. Would you mind to further elaborate on the unknown output that you are referring to in the initial description? Some screenshots will be helpful for further understanding.

    4. Mind share with me the CIC IP configuration ie .ip file will be helpful.

    5. Just wonder if you have had any chance to try simulating the example design generated by the IP to see if the simulation is able to run? ONe of the things on the to do list