Forum Discussion
XQSHEN
Occasional Contributor
Occasional ContributorWarning of timing analysis of UniPHY IP
Intel IP was used and automated generated SDC file was used. Should I do any action on these warnings from timing analysis? PLL clock mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[0] ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
You may refer to the KDB: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd12102013_751.html
It is recommended that you use a dedicated clock input pin that is directly routed to the memory controller reference clock input.
Thanks
Best regards,
KhaiY
KhaiChein_Y_IntelRegular Contributor
Regular ContributorHi,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
Best regards,
KhaiY
