Forum Discussion
Altera_Forum
Honored Contributor
11 years agoI've tried 150MHz system clock for the scaler instead of 100MHz, but it did change absolutely nothing. The output image shows the same problem and also all signals at the simulation look identical including overflow getting set during input line 22, except the alt_vip_cl_scl_0_dout_ready signal going periodically low since the datarate is now lower than the clockrate.