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Altera_Forum
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10 years ago

VIP Clocked Video Out Problem

I am having some problems with the VIP CVO IP. My QSYS core frequency is 100Mhz But my CVO IP output must run at a different frequency. Initially I used 44.8Mhz And it seemed to work ok. H...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Yes, it is the Color Plane Sequencer. I am using the LPDDR to store an image which is read by the Frame-Reader, passed on to the Color Plane Sequencer and from there to the Clocked Video Output. This is a reloadable pattern generator. I now have only one clock of 89.6Mhz. To get the image into the LPDDR I use an External But Bridge which is controlled the SW on the PC via an SPI module-to-USB. The Color Plane Sequencer is the only module that requires a license. I was told that I have to buy the license for the VIP set.

So I want to design my own Color Plane Sequencer. Is there a template/example for developing your own IP. I now added a NIOS II to the design and it runs SW. I tried to add the SD_Card_Avalon_interface. QSYS came back with the error: Altera_UP_SD_Card_Memory_Block.qip,cmp,bsf not found... This project is going to be axed soon if I don't solve these problems.