Honored Contributor
Honored ContributorEven if it fit, you don't need to cache all of the frame in M9K.
After you have it implemented, it will be easier to experiment with the trade off of reduced M9K use vs. increased inefficiency in the DDR2 access. But for example, bursts of 64 pixels at a time 480 x 64 x 16bpp = 0.5mbit and burst of 32 pixels only 0.25mbit both of which you ought to be able to fit in those size devices, if you haven't already over committed. Because 480p is so slow compared to your DDR2, you may be able to get away with much smaller (much more inefficient) bursts e.g. 8 pixels.
