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Altera_Forum's avatar
Altera_Forum
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16 years ago

verilog- parameterized mux

For the life of me I cannot figure out how to generate a parameterized mux in verilog... I understand how to generate, say, a 4:1 MUX of "N" bits wide... But I am trying to generate an N:1 mux...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Old post, but wondering if this ever synthesized? For me, Quartus synthesis errors out on the line:

input [clogb2(CHANNELS-1)-1:0] sel,

Stating:

Error (10140): Verilog HDL error at param_mux.sv(6): range index is not constant

(I just added another parameter for SEL_WIDTH, and used that, forcing the user to manually enter this value. It's easy enough to do, but not ideal...)