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I hope I'm not doing your homework for you. One of the shortcomings of Verilog is the inability to generate ports. So you have to bring the input in as a bus.
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Hahaha.. no, you're not doing your homework for me. Truth be told it's a project I've been working on for a customer for about three months, and this is the last piece to the puzzle (the rest of the project is all done and working just fine) that I just can't seem to crack.
I will admit to only a few years of experience with verilog, so your code snippet has a few curiosities in it that I'll ask below.
genvar ig;
wire input_array +:CHANNELS-1];
assign out = input_array;
generate
for(ig=0; ig<CHANNELS; ig=ig+1) begin: array_assignments
assign input_array = in_bus+:WIDTH];
end
endgenerate
I am not familiar with a "+" in the port width. A very quick google indicates maybe it's a polarity indicator, but that doesn't help me much -- can you explain what you're accomplishing by including it and how it would behave if it were excluded?
I see what you're doing with your generate statement now, and feel a bit silly for not thinking of that myself. I was trying to go about it a much different (and obviously more difficult) way...
I will mess around with your code snip and report back how it goes..
thanks again,
..dane
Honored Contributor
