Forum Discussion
Altera_Forum
Honored Contributor
12 years agoIt might have something to do with the LED_test process not being synchronous. You put clock_50 in the senstivity list, but you didnt follow the template:
process(clk)
begin
if rising_edge(clk) then
--do sync stuff
end if;
end process;
You just made an asynchronous process that would look synchronous in simulation - therefore simulation synthesis missmatch.