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jjang's avatar
jjang
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4 years ago

using modelsim simulation -> "Avalon® Verification IP Suite Design Example"

i Tried below Steps using Attached zip files - Intel FPGA Starter Edition 10.5b (modelsim) At the step 7, script Line#6 vlog -novopt -reportprogress 300 -work work ./slave_bfm_sopc.v ...
YEan's avatar
YEan
Icon for Contributor rankContributor
4 years ago

Hi there,

The slave_bfm_sopc.v in do file has to changed to slave_bfm_sopc.sopc because there is only slave_bfm_sopc.sopc in ug_avalon_verification file.

Thanks,

Ean