Forum Discussion

Gsus's avatar
Gsus
Icon for New Contributor rankNew Contributor
7 years ago

Using a different mem_ref_clk on an EMIF IP than the recommended

Hi , We are doing a relatively complex design on which we are running into timing issues in the emif_usr_clk clock domain. We really need to get the functionality of the design sorted out so we were...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Gsus,

It is recommended to use the fastest possible PLL reference clock frequency because it leads to better jitter performance. Selecting a slower frequency will impact performance. Hence, we recommended user to use the default value by check the "Use recommended PLL reference clock frequency" option.

Thanks

Regards,

NAli1