Understanding Additional IP Interface Signals

Hi,

I think I found the specific signal interface to my hard processor system. I figured out that QSYS seems to generate also a .bsf file, which can be opened, and within this block assistent the specificly required signals can be read out.

The second mistake I did, initiallly - working with 2 .vhd files only - I made a third .vhd file as top level description. When made the component under QSYS, including one of the 2 .vhd files, the resulting .qip component got another different name, which I did not update in the top level .vhd file. I still refered to the .vhd file, which was actually inside the .qip.