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Altera_Forum
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11 years ago

Unable to get 64 bit PCIe Address Headers ( only 32bit addresses are possible )

Hi. We have to a PCIe HIP Root Port in a Cyclone V FPGA. We need to use 64 bit addressing to support the needs of our project. We are using the Avalon-MM interface connection , x 4 lane and are...
Altera_Forum's avatar
Altera_Forum
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11 years ago

We are having a similar problem in both regards with a Cyclone V HIP PCIe Avalon MM endpoint, Gen 1x1. When we request a 64-bit address >4GB, the Slave i/f (TXS) on the PCIe accepts the request but when you capture the TLP that gets generated it is a 32-bit Memory Read Request TLP and with the upper 32-bits zeroed out.

We are also having problems accessing the CRA registers as when I do a read dump all data comes back 0's. However It appears that I can write the CRA because for 64-bit addressing and MSI-X capability you have to set bits 2 and 3 in the cmmd reg (offset x04). I wasn't able to generate an MSI-X until I set these bits so it must have accepted them at least one of them.

I have open SRs on both these issues with Altera but no solution as of yet. In the meantime, for the CRA issue you might want to check out solution ID rd03062014_662 if you haven't done so already. It didn't work for me but others have said it does. Hope this is a configuration issue and not systemic. Good luck.