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Altera_Forum
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11 years ago

Unable to get 64 bit PCIe Address Headers ( only 32bit addresses are possible )

Hi. We have to a PCIe HIP Root Port in a Cyclone V FPGA. We need to use 64 bit addressing to support the needs of our project. We are using the Avalon-MM interface connection , x 4 lane and are...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Some additional information/comments to go with first post

We are unable to write ( change) the Prefetchable Memory Limit and Prefetchable Memory Base field in the Root Port Type Configuration Register ( 24h) .

Read back of Configuration Register 24h results in 0x00000000. Thus, the nibbles which indicates 32b or 64b operation is set to 32b for both the Prefetchable Memory Limit and Prefetchable Memory Base

There is no field in the PCIe HIP Avalon-MM GUI to set the Prefetchable memory size ( Disable, 32b address, 64b address), unlike the Function 0 tab in the PCIe HIP Avalon- ST GUI.

We do have the field of " Address Width of Accessiable PCIe memory space" in the PCIe HIP Avalon-MM GUI set to 64 .

Thanks

Larry