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GDagi1's avatar
GDagi1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Unable to enable RX_TNA and TX_ENA bits (Triple-Speed Ethernet IP)

Hi all, I'm working with the Triple-Speed Ethernet IP and currently am in the process of setting up the MAC register space. I am following the order found in 5.3.1 of the Triple-Speed Ethernet User...
  • GDagi1's avatar
    GDagi1
    5 years ago

    I believe to have solved the issue. Through prior experience with Intel IP, I had thought to implement a counter to remain in the writing state, as it may take some time for this update to complete. I now see these bits go high. I could not find this explicitly stated within the Triple Speed IP User Guide.

Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,


It's good to know you have solved the issue.


One thing to take note is the step 2(E) in TSE user guide doc section 5.3.1.

  • You need to wait for SW_RESET bit to clear (change from 1 to 0) before you assert TX_ENA and RX_ENA in step 2(F)


Aright, I am now setting this case to closure.


Thanks.


Regards,

dlim