Two Avalon ST Interfaces comparison

Yes this will limit the flow on the OLD interface and prevent it from coming in if the FIFO is empty. But if this is happening, you still have an asserted valid signal on your AST_DIFF interface, even if no data is coming, so your output stream will be weird. Second, if you do it this way you need to be sure that the FIFO is protected against a read operation when empty. It is a parameter that can be adjusted in the megawizard. Without the protection you can have garbage results from the FIFO if the fifo_read signal is asserted while it is empty.

But yes, it would be a lot easier to remove the FIFO. As I said, just add a "Avalon ST single clock FIFO" in QSYS/SOPC Builder, and in your component you'll just have to handle the ready and valid signals.