Two Avalon ST Interfaces comparison

There could be a problem with your fifo_read signal. You only tie it to VALID from AST_OLD, which means that it could be 1 even if there is no data in the FIFO. fifo_read (and AST_DIFF_VALID) should be AST_OLD_VALID AND not_empty. Other than that, you may end up in a cycle delay between the two streams.

I think it would be easier if you got rid of the FIFO, and use a ready made "Avalon-ST Single Clock FIFO" on the AST_NEW interface in QSYS/SOPC Builder. That way your custom component doesn't have to control a FIFO and just has two sinks and one source, with direct cabling. It should be easier to get the synchronization right.