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Altera_Forum
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15 years ago

TSE or SGDMA related problem with concurrent tx and rx

Hi, Premise: I don't know if this problem is actually related to tse or sgdma; maybe even to Nios tse driver, although I don't think so. I'm sending and receiving Ethernet packets using t...
Altera_Forum's avatar
Altera_Forum
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15 years ago

The other problem with that code is that it is generating a gated clock for the MAC. It isn't recommended and can lead to problems. I would rewrite the converter to use two clocks generated from a PLL instead. Unfortunately I don't have any card with a RMII PHY so I can't help you.

There seems to be a Verilog code posted here (that obviously needs some serious reformatting): http://www.opencores.org/forum,ethernet%20mac,0,1407. I don't know if it works, and I find it rather strange to use two clocks in the sensitivity list. I'm not sure it is synthesizable.