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SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

TSE IP - SGMII output clock

Hello, I'm using an Arria V FPGA with an TSE IP. The IP is configured for PCS only with SGMII output. By definition, an SGMII interface has a differential data signal and a differential 625 MHz ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,


I am setting this case to closure since I didn't hear back further from you since my explanation in early July.


I hope I have cleared your doubt.


Thanks.


Regards,

dlim