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SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

TSE IP - SGMII output clock

Hello, I'm using an Arria V FPGA with an TSE IP. The IP is configured for PCS only with SGMII output. By definition, an SGMII interface has a differential data signal and a differential 625 MHz ...
SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I'm sorry but this doesn't answer my question.

I'm using the TSE IP with GXB. The txp and rxp is are serial SERDES pins.

But where is the 625 MHz clock that's supposed to be sent to the external device?

I expect the data to be sent together with this clock (source synchronous).

Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Sorry, I didn't explain it clearly.

When you enabled GXB in TSE IP, you are operating in High Speed Serial Interface mode, not really in SGMII mode.

For serial interface application, the clock is already embedded inside the data bus itself. Therefore, you don't need extra sync clock anymore.

Attached is the screenshot of Intel FPGA dev kit board External PHY chip connection and PHY chip datasheet explanation.

I hope I clear your doubt this time.

Thanks.

Regards,

dlim