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dtwolf94's avatar
dtwolf94
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3 years ago

TSE IP - Cyclone 10GX SGMII Interface with External PHY

Hello,

I am trying to setup the TSE IP to connect to an external PHY through SGMII and I am unable to connect at 1000Mb, the auto-negotiation on the external PHY resolves to 100Mb. I am trying to confirm the IP setup was done correctly as part of our debug of this issue and gets some questions related to the IP clarified.

I have the IP core set to 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS, GXB transceiver type, and have enabled SMII bridge. We have initialized the IP based on the steps outlined in section 5.3.2 of the IP User Guide and have read back out the registers to confirm they match.

I am looking for clarification on the difference between SMGII MAC and PHY modes? I haven't found a clear explanation of which mode I should be using or when to use one vs the other?

We have also observed in the PCS control register that the speed is 1G, but our link speed on the external PHY indicates the speed is 100M. Both sides show that SGMII Auto-Negotiation passed, so I do not understand how the speed can be different?

Please let me know if I can provide any other information or if there is anything else I can check to confirm the IP is setup correctly.

Thank you,

Daniel

9 Replies

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
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    3 years ago

    Hi Daniel,


    The difference between SGMII MAC mode & SGMII PHY mode is,

    when SGMII MAC mode is enable, TSE IP will ignore the value in dev_ability register and automatically sets the value to 16’h4001 whereas in SGMII PHY mode you can set the dev_ability register value.

    Kindly look into TSE IP user guide page 102 for more details.


    As you said that the observed speed is 1G in the PCS control register, but link speed on the external PHY indicates the speed is 100M. Have you checked the PCS Control register bit 6 and 13(speed_selection). It has to be set to 10 in order to set the speed to 1G. Refer to page 99 for more detail on PCS control register bit.


    Kindly do let me know if it helps.


    Regards,

    Pavee






  • dtwolf94's avatar
    dtwolf94
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    3 years ago

    Pavee,

    I have read the sections if the user guide you have referenced. I did not find any information as to which mode I should be running in for the setup I described in the original post though. How do I know which mode to run in so I can set bit 5 in the PCS IF_Mode register correctly?

    Per the user guide the speed_selection bits in the PCS Control Register are read only, so I am unsure how these can be set? They appear to just indicate the status of the speed.

    Thank you,

    Daniel

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
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    3 years ago

    Hi Daniel,


    The use of PHY or MAC mode depends on Auto negotiation on your design. You should enable PHY mode if you want to advertise the link speed and duplex mode to the link partner.

    Kindly refer to page 69 for more detailed info.


    I have mentioned the speed_selection register bit for your debug purpose to ensure the bit are set correctly for 1G.

    Link speed is set to Gigabit except for configurations that contain Small MAC. For Small MACs, the default speed is 100 M. So I'm not quite clear on how it can be reduced to 100M. Kindly do let me know how do you confirmed the speed is 100M so that I can debug further.


    Regards,

    Pavee



    • dtwolf94's avatar
      dtwolf94
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      3 years ago

      Pavee,

      Thank you for clarifying the two modes. The speed_selection register indicates the link speed is set to 1G. The 100M is the copper speed, which I have see in the PCS Partner_Ability register and in the external PHY status registers. So my confusion is how can the link speed be set to 1G in the PCS, but the link partner be advertising 100M Copper speed? Perhaps my confusion is from understanding the difference between the link speed and the copper speed? I assumed they must agree with each other in terms of speed.

      I have attached a PCS register dump which indicate the speeds mentioned above.

      Thank you,

      Daniel

      control 4416
      status 169
      phy_identifier1 0
      phy_identifier2 0
      dev_ability 16800
      partner_ability 54273
      an_expansion 3
      scratch 0
      rev 4868
      link_timer1 3392
      link_timer2 3
      if_mode 3

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
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    3 years ago

    Hi Daniel,


    Apologize for the delay. Just for further clarification, so which mode are you using for the design, PHY mode or MAC mode?


    • dtwolf94's avatar
      dtwolf94
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      3 years ago

      Pavee,

      We are using MAC mode.

      -Daniel

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
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    3 years ago

    Hi Daniel,


    Since you're using MAC mode, the TSE IP ignores the value in the dev_ability register and automatically sets the value to 16’h4001. Once auto-negotiation completes, TSE IP speed will be resolved based on the value in the partner_ability. The partner_ability register is received from the link partner during the auto-negotiation process.


    There are few options to check on auto negotiation:


    1. Make sure that both sides of the link are configured the same way.
    • If one side of the link is set to auto-negotiation, make sure the other side is also set to auto-negotiation.
    • If one side is set to 100/full, make sure the other side is also set to 100/full.
    • Failure may happened if one side of the link has been set to 100/full, and the other side has been set to auto-negotiation

    This may results in one side being 100/full, and the other side being 100/half.

    1. Auto negotiation must be configure in one PHY mode and one MAC mode
    • Auto Negotiation completed but 2 devices run at different speed. It was due to 2 SGMII PCS are configured with Auto Negotiation in MAC mode. In SGMII AN, one PCS must be in MAC mode and the other in PHY mode
    1. Auto Negotiation succeeded with mismatch ability advertised.
    • It happened that "SGMII bridge" option was enabled in parameter setting but SGMII ENA bit of IF_MODE register was set to '0'.
      • The SGMII mode does not disabled if SGMII bridge is enabled in the parameter setting. Hence, Auto Negotiation was done in SGMII mode instead of 1000BASE-X mode. dev_ability and partner_ability registers do not take effect in SGMII mode.

    Regards,

    Pavee


  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi Daniel,


    We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get the support from Intel experts.

    Otherwise, the community users will continue to help you on this thread.

    Thank you.