TSE in SGMII Mode with external FIFO and PLL for PCS Ref Clock

The funny thing for me is that I can get my design to compile with a PLL (100MHz input, 125MHz output) with the PLL outclock connected to the TSE ref_clk -- no errors. For me, I have no signal from the HSMC_REF_CLK (100MHz) that should be utilizing Pin 9 (with HCSL I/O Standard). I've tried two Dev Kits, same thing. I even ask a fellow EE next door to try to test the 100MHz clock signal -- he too cannot get a signal from this clock. Not that it will solve your issue, but will you verify (with a blink program or using signal tap) that you are getting a signal on Pin 9?

Back to your issue, I haven't been able to test any of the theories that are in my head, but one thought that comes to mind... have you tried a clock control block (ALTCLKCTRL) prior to your PLL?

References:

http://www.altera.com/support/kdb/solutions/rd03302012_430.html

http://www.altera.com/support/kdb/solutions/rd09252012_453.html

http://www.altera.com/literature/ug/ug_altclock.pdf