TSE in SGMII Mode with external FIFO and PLL for PCS Ref Clock

I'm guessing that internally the TSE, when interfaced with transceivers, does something different with the global and or regional clock assignments depending on whether its an internal or external FIFO. You can look at this in the generated code for the TSE.

If you instantiate the PLL at the top level with the mega-wizard (i.e. outside of QSYS) then you should see options for specific location assignments auto/top/bottom/left/right for the PLL, or in any case I seem to recall seeing such options for the cyclone III.

You might also have a look at the Altera document related to PLLs and global clock routing resources in the Cyclone V.