TSE in SGMII Mode with external FIFO and PLL for PCS Ref Clock

I am going to go out on a limb, based on issues with clock control blocks and a CLKENBL signal, and guess that there is a resource usage limitation in your device, presumably a Cyclone V, related to routing for clock control blocks. Perhaps the next step is to look at the resource consumption report in the compilation output specifically at the PLL and clock control block usage. Perhaps you need to try to combine PLLs or use a PLL on the same side of the device as the transceiver?