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Altera_Forum
Honored Contributor
12 years agoI didn't put any constraints on the i/o pins to the PHY.But I watched the timing of MII interface(tx_clk,m_tx_d,m_tx_en,m_tx_err,rx_clk_0,m_rx_d,m_rx_en,m_rx_err,m_rx_col,m_rx_crs ).
They were right.