TSE (Ethernet) - Core does not transmit data on RGMII TX, rest works perfectly fine

I experienced a similar issue, now solved, the problem was with timing of data and clock signals. You need to constrain the design correctly to make the data edge-aligned or center aligned depending on your PHY settings (described aHP mode or 3COM). The key to solving my problem was to run the clock signal through an ALT_DDIO buffer rather than directly to the output pin. This means the clock is routed through the same logic as the data, which should help with timing closure (this is not an obvious thing to do from reading application notes!!!)