Forum Discussion

SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

TSE - PCS only internal loopback problem

Hello, I'm using the TSE core in a PCS only configuration on an Arria V FPGA. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf Data is being sent from my...
SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

So this means that if the receiving logic (that's connected to the TSE IP) MUSTN'T be designed to ALWAYS accept a 7 byte 0x55 preamble ?