Honored Contributor
Honored ContributorI should have asked for the VRam.v file instead of the .qip file but I can see from the port list how the RAM was configured.
Your code looks fine except that the data_a input port on the RAM is not connected. Since you're using port A as read-only you should tie data_a off as 16'h0. The fact that writes now work in simulation says that your logic is ok, so this must be a synthesis issue. Is there anything in the synthesis reports about this RAM? At a minimum you should get a warning about the unconnected data_a input. Maybe the synthesis tool is doing something stupid because of that dangling input? I would tie off data_a and try again. If it still doesn't work I would try SignalTap. Instrument the VRam inputs and outputs and see what's happening in hardware. The final step would be to open a service request with Altera. One side comment: Doing the read address math for address_a at instantiation is not very good form. It would be better to declare a signal (wire or reg) for that read address and assign it separately where you can add some comments about what you're doing. Good luck. Bob
