Forum Discussion
FFAA
New Contributor
1 year agoTriple Speed Ethernet
I just finished generated the IP and Instantiated into a stand alone design. at This time it had nothing in the design but only the IP with the top level wrapper.
I compiled it and it gave me this errors ?
Please help.
thanks
.
3 Replies
- FvM
Super Contributor
Hi,
you are apparently ignoring requirements. PLL clock input must be driven by dedicated clock input. - paveetirrasrie_Altera
Frequent Contributor
Hi,
Based on previous reply, does that answer your query?
Regards,
Pavee
- paveetirrasrie_Altera
Frequent Contributor
Hello,
We didn't hear from you since last update. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread.
Thank you.