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yairShapira's avatar
yairShapira
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Triple speed ethernet ip on cyclon v resource allocation

Hi All. I have built an 8 port ethernet mac with sgmii pcs and embedded pma using the triple speed ethernet ip from the quartus 18.0 IP Catalog. I am using cyclon V gx. after connecting everythi...
  • Deshi_Intel's avatar
    Deshi_Intel
    5 years ago

    Hi Yair,


    Yup, for CV TSE IP, CMU PLL is the only supported option right now.


    Ya, sure, feel free to explore other IP as well. It may comes with different PLL support structure.


    I believed the enquiry on TSE IP is addressed. Feel free to post new forum thread if you have questions on other Intel IP solution.


    For now, I am setting this case to closure as Intel support structure is on a case by case basic.


    Thanks for your understanding


    Regards,

    dlim


Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hey,


No worry. FPGA design indeed is complex and not easy to master.


So, just wonder is the TSE fitter issue resolved now once you switch to bigger FPGA device or you cut down on TSE channel usage ?


Thanks.


Regards,

dlim


  • yairShapira's avatar
    yairShapira
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi.

    As I need only 7 channels for this project, I skipped ports 1 and 4, so they can be used as CMU, and now it fits o.k. I am trying to get everything to work and then I will re-design my circuit.

    I am still wondering if there is a way to use the FPLL instead of the CMU (as is seems like valid option in the Cyclone v transceiver hand book) maybe with a different IP ?

    Thanks

    Regards

    Yair.