Forum Discussion
New ContributorTriple speed ethernet ip on cyclon v resource allocation
Hi Yair,
Yup, for CV TSE IP, CMU PLL is the only supported option right now.
Ya, sure, feel free to explore other IP as well. It may comes with different PLL support structure.
I believed the enquiry on TSE IP is addressed. Feel free to post new forum thread if you have questions on other Intel IP solution.
For now, I am setting this case to closure as Intel support structure is on a case by case basic.
Thanks for your understanding
Regards,
dlim
Regular ContributorHi Yair,
It's good design practice to always test out design in Quartus fitter compilation first before proceed with board design.
Only channel 1 and channel 4 have "centralize clock network" to spam the clock network to clock all 6 channels within one transceiver bank.
- You can read more about Cyclone V transceiver clocking in chapter 2 of below user guide doc
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf
Now to your questions.
1. Do I have to use the CMU ? I have seen in the handbook that there is an option to use FPLL, but there is no flexibility in the TSE Wizard.
- I am not quite sure where you see it but anyway the doc most of the time don't explicitly speel out the supported feature is for which FPGA product family.
- Same IP may exist across different FPGA product family but the IP feature support maybe different due to changes of FPGA architecture
- To be safe, always launch the specific IP in your desired FPGA device (Cyclone V in your case) then check what's available support option. As you can see that only CMU PLL option is available in Cyclone V TSE IP
2. If I must use channel 1 and 4 as CMU, Then how should I connect them in the PCB ? leave them open ?
- You can always refer to FPGA pin connection guideline to check out how to connect FPGA pins on board
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf
- Page 21 mentioned unused GXB_Tx pin can be left float while unused GXB_RX pin can connect to GND
- I advise you to add series zero ohm resistor before short channel1/4 RX pin to GND. Then you will have the flexibility to either short it to GND or remove resistor to left the pin float
Thanks.
Regards,
dlim
New ContributorMany Thanks Dlim.
Yes, as a beginner in FPGA complex IP's, sometimes I learn things the hard way :-).
I Thought that I have the FPLL Option to clock the transmitter, because I saw it in the Cyclone V transceiver handbook (device handbook volume 2):
"Transmitter PLL
In Cyclone V GX/GT/SX/ST devices, there are two transmitter PLL sources: CMU PLL (channel PLL) and
fPLL. The channel PLL can be used as CMU PLL to clock the transceivers or as clock data recovery (CDR)
PLL" (page 1-21).
So, I thought , if the TSE doesn't support it, may be I could use a different IP.
Thanks again
regards
Yair.
