Forum Discussion
Triple speed ethernet ip on cyclon v resource allocation
- 5 years ago
Hi Yair,
Yup, for CV TSE IP, CMU PLL is the only supported option right now.
Ya, sure, feel free to explore other IP as well. It may comes with different PLL support structure.
I believed the enquiry on TSE IP is addressed. Feel free to post new forum thread if you have questions on other Intel IP solution.
For now, I am setting this case to closure as Intel support structure is on a case by case basic.
Thanks for your understanding
Regards,
dlim
Hi Yair,
The reason behind is there is no standalone CMU PLL design block.
It's basically a dual function shared design block where user can choose to either use it as
- CDR design block of Rx channel
- or as CMU PLL
So if user choose to use as CMU PLL, that RX channel can't be used anymore
Else if user choose to use it as Rx channel then there is no more CMU PLL
Thanks.
Regards,
dlim
- yairShapira5 years ago
New Contributor
Hi.
So I finally managed to fit 7 channels. and found that it is possible only when I leave channel 1 and 4 free. So the Quartus uses channel 1 and 4 as CMU.
Unfortunately this dose not feet my already made PCB, So I will have to make another layout. I have 2 questions :
1. Do I have to use the CMU ? I have seen in the handbook that there is an option to use FPLL, but there is no flexibility in the TSE Wizard.
2. If I must use channel 1 and 4 as CMU, Then how should I connect them in the PCB ? leave them open ?
Thanks for all your help Dlim , really appreciate it.
Regards
Yair