Forum Discussion
New ContributorTriple speed ethernet ip on cyclon v resource allocation
Hi Yair,
Yup, for CV TSE IP, CMU PLL is the only supported option right now.
Ya, sure, feel free to explore other IP as well. It may comes with different PLL support structure.
I believed the enquiry on TSE IP is addressed. Feel free to post new forum thread if you have questions on other Intel IP solution.
For now, I am setting this case to closure as Intel support structure is on a case by case basic.
Thanks for your understanding
Regards,
dlim
Regular ContributorHi Yair,
Is your TSE IP design using CMU PLL ?
If yes, then I suspect certain transceiver RX channel is being converted to become CMU PLL to clock TSE IP. This could explained why total consumption is more than 8 channels.
You can reduced your design TSE IP count to lower channel like maybe 4 channel, get a passing fitter compilation, then study the fitter report to see how many CMU PLL is being consumed
Thanks.
Regards,
dlim
yairShapiraHi.
Thanks for your reply.
Yes , it is a CMU PLL. For Cyclon V , The TSE uses only CMU PLL. However , I was thinking that the CMU PLL Is a part of each GBX transceiver. So why should he dedicate a transceiver to be used as a PLL...
Any way instead of using an 8 port block, I am trying to use single port blocks, and grow gradually until I reach the 7 ports I need. for now I fitted 2 successfully. and currently the usage is :
2/9 Standard RX PCSs
2/9 PMA RX Deserializers
2/9 Standard TX PCSs
2/9 PMA TX Deserializers
3/9 Channel Pll's
Thanks for all your help
Yair.
