Triple speed ethernet IP core don't receive the RGMII data?

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Since your error is 4-bits wide, and since RGMII is a 4-bit wide DDR bus, I think you need to look closer there.

Is the problem something simple like you didn't add the timing constraints for the 2nd port? Double check for timing violations anyway.

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Bit 7 to 4 of CRC-32 field of every received packet becomes a "4" while all other bits is exactly correct. How timing violations could cause such constant error? And, there is still an error after adding some timing constraints to RGMII interface.