Triple speed Ethernet & SGMII

Hi,

The extra 0xD5 value looks like a start frame delimiter (SFD) packet that byright TSE MAC should removed. User should see destination address as first packet coming our from TSE RX path to Avalon ST interface.

You can refer to TSE user guide doc (page 195, Figure 82 : MAC Ethernet Frame Format" for detail.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug_ethernet-19-4-0.pdf

I think you need to slowly trace back the RX path to see where does this extra 0xD5 come from

• Eg : External RX PHY -> TBI -> TSE PCS SGMII -> GMII/MII -> TSE MAC -> Avalon ST bus
• For a start, maybe you can add in MII interface bus (since you are running 100M) into signal_tap to check on the receive data first. Refer to (page 107, figure 46) to check out MAC interface signals list that contains the MII interface bus
• This helps to isolate whether TSE MAC is receiving correct Rx data in the first place or not

You can also generate TSE simulation example design project using your existing TSE IP setting. This will give you extra flexibility to look into TSE IP interface signals to understand the expected behaviour

Thanks.

Regards,

dlim