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SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Tri-Speed Ethernet IP - Link Status up

Hello, I'm using the Tri-Speed Ethernet IP on an Arria V FPGA. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf The IP is configured as "PCS Only". Aft...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi

Yes, the link sync is up if it can receive 3 common characters. From the simulation, I can also observe the led_link is asserted before the register initialization.

Regards -SK