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SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Tri-Speed Ethernet IP - Link Status up

Hello, I'm using the Tri-Speed Ethernet IP on an Arria V FPGA. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf The IP is configured as "PCS Only". Aft...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Thank you for the clarification.

The register at address 1 is reporting the correct info since the led_link is up. The led_link is up probably is because of the TSE's transceiver is connecting to the onboard PCB traces, and the CDR can be locked after power on if another end of the transceiver is also active.

Regards -SK