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SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Tri-Speed Ethernet IP - Link Status up

Hello, I'm using the Tri-Speed Ethernet IP on an Arria V FPGA. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf The IP is configured as "PCS Only". Aft...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

There is a Link Synchronization block in the PCS, this block is to ensure CDR is stable and word alignment. Ethernet can achieve link if received 3 common characters (K28.5/D16.2).

To confirm if this is not the register at address 0x01 reporting the wrong info. It will be a great help if you can confirm the led link status signal. Besides, please unplug any connector to the TSE IP ethernet port to confirm if this can read out 0x89.

Regards -SK