Occasional Contributor
Regular ContributorHi,
For 1) In a Cyclone 10 GX Transceiver Native PHY configured with:
the tx_control and rx_control ports are generally not exposed when “Enable simplified data interface” is ON. Even with the simplified interface OFF, those control ports only appear for PCS modes that actually use explicit per-byte control (e.g., 8b/10b streaming). Most Enhanced PCS profiles (often 64B/66B-based) handle control internally, so tx_control/rx_control do not appear at all.
Your observation— not seeing rx_control/tx_control when the simplified data interface is ON—is expected for Enhanced PCS configurations.
For 2) For the Basic or Custom mode, 2 LSB bits are used to identify data or control word.
Hope this helps.
Regards
Occasional ContributorHi Ash,
Thanks for you reply.
You know we migrate from Arria GX to Cyclone 10 GX now. We used exactly per-byte control in our previous application when using Arria GX, however, the parallel data width was limited to 16-bit.
Now, we have change to expand our parallel data bit width from 16-bit to 32-bit on Cyclone 10 GX devices. We still don't use any protocol, and transfer data from point to another point. Just change parallel data bit width and increase the serial data rate. In this case, we chose to use Enhanced PCS, but how can we to align word boundary in this case?
Best Regards
