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Jonni's avatar
Jonni
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7 years ago

Timing violations when configuring PCIe HIP @ Gen-3 x8 256bit

Hi Intel, We are having timing violations reported by TimeQuest when using PCIe HIP configured as Root Port @ Gen-3 x8 256bit using your downloadable GHRD (w/ pcie) files for Arria 10 SOC DevKit as ...
KennyT_altera's avatar
KennyT_altera
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7 years ago

Yes, changing the quartus version will yield different result.

I see that your report failing is soc_inst|pcie256_0|pcie_a10_hip_avmm|coreclkout

You have to check where does this clock connected to? Usually it would user logic clock.

  • Jonni's avatar
    Jonni
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    7 years ago

    Hi,

    I have attached one of the paths reported by TimeQuest and a screenshot of Timequest while viewing (RAR file). The path chosen has the longest delay among the rest for "SETUP".

    I tried reporting 1000 paths, and even 10k paths, but TimeQuest filled them all up with violated paths.

    From the looks of the report, seems that the components outside connected the PCIe HIP (particularly, the bridges) are the ones containing the violated paths. Do you have any suggestions as to how we should get around them?

    Thanks!