Forum Discussion
ChunyeHong
New Contributor
6 years agoTiming debugging required on Quartus build dependent packet issue if Seriallite II
I have been asked to open a new issue. Here is the thread. Thank you
Serialite II Issue
We have 4 copies of SerialLite II IP core in ou...
KhaiChein_Y_Intel
Regular Contributor
5 years agoHi,
Do you see timing violation in the design? Could you share the design.QAR file for investigation?
Thanks.
Best regards,
KhaiY
ChunyeHong
New Contributor
5 years agoHi,
No timing violation in the timequest report. I can not share the design because IP and security issue.
Thanks,
Chunye