Throughput Efficiency with half-rate DDR2 controller

The SOPC automatically generated arbitration between the different memory bus masters is not efficient.

You might want to look into a block called Multi Port Front End:

http://www.altera.com/literature/an/an637.pdf

This should be able to handle the arbitration in a more efficient way and thus give you

more memory throughput.

You want each master to be able to issue and complete a burst of data (reads or writes) before switching off

to the next mm-master. The larger the burst size, the more throughput to SDRAM you should see.