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Altera_Forum
Honored Contributor
Honored ContributorThroughput Efficiency with half-rate DDR2 controller
I have been developed system which performs simultaneous writing and reading of the same DDR2 RAM (reading from the first half, writing to the second half). Read and write data (32 bit width) are dig...
Altera_ForumHonored Contributor
Honored ContributorThe SOPC automatically generated arbitration between the different memory bus masters is not efficient.
You might want to look into a block called Multi Port Front End: http://www.altera.com/literature/an/an637.pdf This should be able to handle the arbitration in a more efficient way and thus give you more memory throughput. You want each master to be able to issue and complete a burst of data (reads or writes) before switching off to the next mm-master. The larger the burst size, the more throughput to SDRAM you should see.
