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SPols
New Contributor
New ContributorThe DDR2 Controller with UniPHY has a port called "afi_reset". What causes this signal to assert? We are experiencing this signal asserting on a small subset of custom fpga boards. We are trying to debug the exact cause.
We have made a set of custom boards incorporating the Altera chip as documented in the information of the form. We have an issue directly related to the DDR2 controller on 2 of the 12 boards we have ...
NurAida_A_Intel
Frequent Contributor
Frequent ContributorDear SPols,
Thank you for joining this Intel Community.
The afi_reset signal will assert based on 2 conditions:
- PHY is reset
- PLL loses lock : This indicate that your afi_clk is not stable yet thus it will assert the reset signal until the PLL is locked.
For more details, you can refer to this user guide : https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/external-memory/emi_ddr3up_ug.pdf
Hope this helps
Regards,
NAli1
SPolsHi NAli1,
Thank you for getting back to me. Do you know what can cause a reset to the PHY? Also do you know why the PLL might lose lock? I have two circuit boards, with the exact same hardware and Altera firmware but this issue only happens with one of them. Does anything come to mind?
Thanks
