System Design : MIPI Rx interface to PCIe

Question

hi,

I want to design a system which need to transfer the video data from a camera to a processor,as my processor motherboard doesnt have a MIPI interface i want to tranfer the same through Fpga where i will interface the MIPI Rx IP & PCIe (end point).

my doubts are the following

is it possible to directly interface the MIPI RX output (which is in Avalon ST ) and the PCIe (endpoint configured as Avalon ST)?
in some other MIPI ip i found that the interface for control registers are through Avalon MM,then how can i access the data which is going out of the MIPI-IP?
is there any reference design available so that i can interface the mipi-ip output to some memory and then it will be read by the pcie through avalon MM interface?

please provide some me suggestions,

thanks in advance,

sengkok_l_intel · Answer

Hi Sir,

1.	No, this can’t directly interface the Avalon ST between MIPI RX and PCie ST since the data format or standard is difference. You have to decode and translate it if you wanna use the PCIe to transmit the date. Please refer to the PCIe IP avalon ST user guide for more detail info.
2.	If this is Avalon MM slave interface, then you can use any Avalon MM master port to access it.  For example, Nios II processor, or you can create a state machine to read it out. 
Please refer to the Avalon specification for more detail. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
3.	The following example design of PCIe may be helpful to you
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an829.pdf
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an456.pdf

Regards -SK

matt1 · Answer

hi SK Lim,thanks for the reply.if I need to interface the Avalon ST of MIPI CSI2 to a buffer for eg: on chip memory and the read part of the buffer is an Avalon MM interface of PCIe endpoint then how to find the size of the buffer?if you have some reference  can you please share it.thanks and regards

sengkok_l_intel · Answer

​Hi Matt, The buffer size needed is based on your application requirement. The On-chip Memory size can be configure from the IP GUI. Regards -SK

matt1 · Answer

Hi,ok thanks.

Forum Discussion

System Design : MIPI Rx interface to PCIe

4 Replies

Recent Discussions

Regarding the TX settings of MIPI CSI2 IP

How to Prevent Agilex 7 F-tile PMA Direct PHY TX Lane Skew

Request for private case.

PCIe Enumeration Failure for CXL IP

Stratix-10G FPGA Transceiver Configuration for Ethernet MAC 100G Controller