Forum Discussion

Vamsi_21's avatar
Vamsi_21
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

System console giving up when running the command "TEST_PHYSERIAL_LOOPBACK 0 1G 1000"

Hi,
I have generated the design example for Low latency ethernet 10g mac intel fpga ip-- 10M/100M/1G/10G example design(Arria 10) by following the below document.
https://www.intel.com/content/www/us/en/docs/programmable/683063/19-1-19-1/10m-100m-1g-10g-ethernet-design-example.html

While testing it on the hardware, I am getting the below error from system console.

“error: master_write_32: This transaction did not complete in 60 seconds. System console is giving up.
While executing
“master_write_32 sport_id $address $wdata”
(procedure “reg_write” line 7)
invoked from within
“reg_write $PHY_IP_BASE_ADDR $seq_control 0X111”
(procedure “SETPHY_SPEED_1G” line
invoked from within
“CONFIG_IPORT $speed_test”
(procedure “TEST_PHYSERIAL_LOOPBACK” line 10)
invoked from within
TEST_PHYSERIAL_LOOPBACK 0 1G 1000”

I have changed the USB blaster frequency to 16MHz,6MHz but still I am getting the issue.

Details:

Quartus used : Quartus prime 22.2
Board :Intel arria 10 GX development board
Device : 10AX115S2F45I1SG.

Below are the clock pin assignments
Name pin assigned
mm_clk 125Mhz BD24 clk_125
ref_clk_1g 125MHz N37 REFCLK_SMA (modified using clk controller).
ref_clk_10g 644.53125Mhz AA37 REFCLK_SFP

Ethernet

45 Replies

Show More
  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Vamsi,


    I sent example design quartus version 22.2 to your email.


    Best regatrs,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Vamsi,


    For the issue about the output is always the same irrespective of 10g/1g speed, burst size and different tests like PHYSERIAL_LOOPBACK and SMA LOOPBACK, I also got the same result as you mentioned after few tries.


    Best regards,

    zying


    • Vamsi_21's avatar
      Vamsi_21
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi,
      I had also gone through the .tcl scripts for the 10g design but was not able to find out the reason for the same output irrespective of different tets.

      For the 100g design you have sent , I am still getting the TTK failed reading phy slave _10000 cannot enable ttk functionality .....

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Vamsi,


    Since the A10 device is too old, it was actually out of our plan and the bug was planned to be fixed in Quartus version 24.2. I now transition this thread to community support. The community users will continue to help you on this thread.


    Best regards,

    Zi Ying