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Altera_Forum's avatar
Altera_Forum
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12 years ago

Stream to Memory sgdma problem

I am having two problems with the sg-dma in my system. My first issue is that the sg-dma ready signal goes low after the first element of streaming data, then returns high on the third. This causes...
Altera_Forum's avatar
Altera_Forum
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11 years ago

If you haven't updated the IP I highly recommend it because I fixed a bug a year or two ago which caused FIFO corruption under some configurations. I forget what configurations are affected but the symptom was that the FIFO inside one of the masters would transistion from empty to full and vice versa which would cause data to be lost or garbage to be written.

The IP is available in Qsys as of 14.0 so if you are using that version I recommend using it instead. Unfortunately the driver isn't available yet so you would have to continue using the old driver.

Also if you want to maximize memory bandwidth I recommend making the DMA wider and using a data format adapter to convert the 8-bit data from the ADC to a wider beat so that the DMA can use more of the memory bandwidth each clock cycle (I'm assuming your RAM isn't 8-bit)