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I am having two problems with the sg-dma in my system. My first issue is that the sg-dma ready signal goes low after the first element of streaming data, then returns high on the third. This causes the second element to be skipped. I am streaming data at the same rate as the sg-dma clock.
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It sounds like the components that are the source of the stream aren't prepared to accept the backpressure from the SGDMA. It's only going to get worse if the SGDMA encounters any contention or other delays (e.g. SDRAM refresh) when it's trying to burst to the memory.
One workaround is you can place an Avalon-ST FIFO right before the SGDMA; the FIFO won't deassert 'ready' until it is nearly full.
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