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rkv's avatar
rkv
Icon for New Contributor rankNew Contributor
5 years ago

Stratix10 P-Tile AVMM IP for PCIe does multiple read requests for a single s/w 64-byte read request

The software is able to do 64-byte single read transaction to on-chip ram by making the BAR region as WC region using the instruction below. __m256i a = _mm256_stream_load_si256 ((__m256i*)mem_base...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Did you observe completion Timeout status is asserted from the Advanced uncorrectable error status register?

Does the latency of “read_data_valid” for 64bytes larger than 32bytes? How long it requires to wait for *_valid signal to assert?


Regards -SK