Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Stratix v PCI Express Hard IP not detected

Hi , I'm using the example design for Stratix V Hard IP for PCI Express geenerated by Quartus prime 15.1 . My pc which uses Intel core i7-3770 is unble to detect it ,aother pc with Intel core...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

What lane rate have you set in the PCIe core? How are you connecting it to the motherboard? (riser cable?)

The core has issues with lane rate negotiation in situations where it has to fall back to a lower speed. For example, when the device is compiled for Gen 2 and is plugged in to a motherboard which supports gen 2, but using say a riser cable which is not of high enough quality, it can cause both ends of the link to try the higher rate, fail because of the riser, but then the FPGA core locks up and fails to fall back to the lower speed and hence not enumerate.